1. Field of the Invention
The present invention relates in general to a method for CPU power management and bus optimization. In particular, the present invention relates to a method for I/O link protocol technology and power management on AMD K8 platform.
2. Description of the Related Art
Legacy I/O bus architectures are widely used in embedded systems because they are low cost and easily implemented using established software and hardware standards. These busses, however, top out at 66 MHz or so. Recently, processors operating at 500 MHz and 1 GHz and up clock frequencies need a faster alternative to these low bandwidth busses.
Lightning data transport (LDT) I/O bus, sometimes referred to hyper-transport (HT) I/O bus, delivers the high bandwidth needed for high performance applications in networking, communications and other embedded applications in a flexible, extensible and easily implemented bus structure. A scalable solution, the LDT I/O bus is capable of providing bandwidth for next generation processors and communications systems. A multivendor standard that is easily implemented, the LDT solution provides a broad selection of bus widths and speeds meeting the power, space and cost requirements of a wide range of embedded systems from low cost desktop workstations to digital consumer applications, communication systems, and networking equipment.
The optimization of LDT I/O bus is achieved through disconnection and reconnection of the LDT I/O bus enabling the LDT I/O bus to perform at desired bandwidth and operating frequency.
FIG. 1 is a flowchart of the optimization of bandwidth and operating frequency of conventional LDT I/O bus. First, LDT bus is initialized by basic input/output system (BIOS) (S1), such as by setting the optimized bandwidth and operating frequency of LDT bus connected between CPU and the Northbridge after booting. For example, the bandwidth of the LDT bus may be initialized as 8-bit, but can be changed to 16-bit after optimization. The operating frequency of the LDT bus may be initialized as 200 MHz, but can be changed to 400 MHz, 600 MHz or 800 MHz after optimization. Here, the optimized bandwidth and operating frequency of LDT bus are set by BIOS. Next, power management resisters of CPU and the chipset comprising a Northbridge and a Southbridge are initialized by BIOS to set the related power setting (S2). Next, an auto-resume timer in the Southbridge is initialized for calculating an elapsed time value (S3). Next, BIOS issues a read request to a Southbridge power management I/O (PMIO) offset 15 h for asserting a signal LDTSTOP# (S4). Here, the asserting of the signal LDTSTOP# transforms a high level signal LDTSTOP# to a low level signal LDTSTOP#. The LDT bus connected between CPU and the Northbridge is disconnected when the signal LDTSTOP# is asserted.
Next, the Southbridge de-asserts the signal LDTSTOP# when the elapsed time value of the timer initialized in step S3 reaches a predetermined value (S5). Here, the de-asserting of the signal LDTSTOP# transforms a low level signal LDTSTOP# to a high level signal LDTSTOP#. Thus, the LDT bus connected between CPU and the Northbridge is reconnected when the signal LDTSTOP# is de-asserted (S6). Therefore, the LDT bus operates at optimized bandwidth and operating frequency set in BIOS. Thus, optimization of bandwidth and operating frequency of LDT bus is completed.
Power management is another important boot process in computer systems. FIG. 2 shows a conventional power management process. First, power management resisters of CPU and the chipset comprising the Northbridge and the Southbridge are initialized by BIOS to set the related power setting (S21). Next, maximum operating frequency and voltage of CPU are obtained from the register FIDVID_STATUS of CPU and stored in the register FIDVID_CTL of CPU by BIOS (S22). Next, an auto-resume timer in the Southbridge is initialized for calculating an elapsed time value (S23). Next, CPU outputs a FID/VID change message to the Southbridge and the signal LDTSTOP# is asserted when the Southbridge receives the FID/VID change message (S24). Here, the asserting of the signal LDTSTOP# also transforms a high level signal LDTSTOP# to a low level signal LDTSTOP#. The LDT bus connected between CPU and the Northbridge is disconnected when the signal LDTSTOP# is asserted. Next, operating frequency and voltage of CPU are changed according to the setting in FIDVID_CTL register (S25). Next, the Southbridge de-asserts the signal LDTSTOP# when the elapsed time value of the timer initialized in step S24 reaches another predetermined value (S26). Here, the de-asserting of the signal LDTSTOP# transforms a low level signal LDTSTOP# to a high level signal LDTSTOP#. Thus, the LDT bus connected between CPU and the Northbridge is reconnected when the signal LDTSTOP# is de-asserted (S27). Therefore, CPU operates at the adjusted operating frequency with the adjusted operating voltage. Thus, power management of CPU is achieved.
Power management of CPU and LDT bus optimization described are performed independently during boot. However, the disconnection and reconnection of LDT bus are performed in both processes. The repeated hardware operation causes booting delay and complicates of boot process.